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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 125 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? high endurance, non-volatile memory segments ? 16k bytes of in-system, self-programmable flash program memory ? endurance: 10,000 write/erase cycles ? 256 bytes of in-syst em programmable eeprom ? endurance: 100,000 write/erase cycles ? 1k byte of internal sram ? data retention: 20 years at 85 c / 100 years at 25 c ? programming lock for self-program ming flash & eeprom data security ? peripheral features ? dedicated hardware and qtouch ? library support for capacitive touch sensing ? one 8-bit and one 16-bit timer/counter with two pwm channels, each ? 12-channel, 10-bit adc ? programmable ultra low power watchdog timer ? on-chip analog comparator ? two full duplex usarts with start frame detection ? universal serial interface ? slave i 2 c serial interface ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? internal and external interrupt sources ? pin change interrupt on 18 pins ? low power idle, adc noise reductio n, standby and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit with supply voltage sampling ? calibrated 8mhz oscillator with temperature calibration option ? calibrated 32khz ultra low power oscillator ? on-chip temperature sensor ? i/o and packages ? 18 programmable i/o lines ? 20-pad qfn/mlf, and 20-pin soic ? operating voltage: ? 1.8 ? 5.5v ? speed grade: ? 0 ? 2mhz @ 1.8 ? 5.5v ? 0 ? 8mhz @ 2.7 ? 5.5v ? 0 ? 12mhz @ 4.5 ? 5.5v ? temperature range: -40 c to +85 c ? low power consumption ? active mode: 0.2 ma at 1.8v and 1mhz ? idle mode: 30 a at 1.8v and 1mhz ? power-down mode (wdt enabled): 1 a at 1.8v ? power-down mode (wdt disabled): 100 na at 1.8v 8-bit microcontroller with 16k bytes in-system programmable flash ATTINY1634 summary rev. 8303bs?avr?03/12 www.datasheet.co.kr datasheet pdf - http://www..net/
2 8303bs?avr?03/12 ATTINY1634 1. pin configurations figure 1-1. pinout of ATTINY1634 1 2 3 4 5 qfn/mlf 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 note bottom pad should be soldered to ground. (pcint1/ain0) pa1 (pcint0/aref) pa0 gnd vcc pc5 (xtal1/clki/pcint17) pc0 (adc9/oc0a/xck0/pcint12) pc1 (adc10/icp1/scl/usck/xck1/pcint13) pc2 (adc11/clko/int0/pcint14) pc3 (reset/dw/pcint15) pc4 (xtal2/pcint16) pa7 (pcint7/rxd0/adc4) pb0 (pcint8/txd0/adc5) pb1 (adc6/di/sda/rxd1/pcint9) pb2 (adc7/do/txd1/pcint10) pb3 (adc8/oc1a/pcint11) (pcint6/oc1b/adc3) pa6 (pcint5/oc0b/adc2) pa5 (pcint4/t0/adc1) pa4 (pcint3/t1/sns/adc0) pa3 (pcint2/ain1) pa2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (pcint8/txd0/adc5) pb0 (pcint7/rxd0/adc4) pa7 (pcint6/oc1b/adc3) pa6 (pcint5/oc0b/adc2) pa5 (pcint4/t0/adc1) pa4 (pcint3/t1/sns/adc0) pa3 (pcint2/ain1) pa2 (pcint1/ain0) pa1 (pcint0/aref) pa0 gnd pb1 (adc6/di/sda/rxd1/pcint9) pb2 (adc7/do/txd1/pcint10) pb3 (adc8/oc1a/pcint11) pc0 (adc9/oc0a/xck0/pcint12) pc1 (adc10/icp1/scl/usck/xck1/pcint13) pc2 (adc11/clko/int0/pcint14) pc3 (reset/dw/pcint15) pc4 (xtal2/pcint16) pc5 (xtal1/clki/pcint17) vcc soic www.datasheet.co.kr datasheet pdf - http://www..net/
3 8303bs?avr?03/12 ATTINY1634 1.1 pin descriptions 1.1.1 vcc supply voltage. 1.1.2 gnd ground. 1.1.3 xtal1 input to the inverting amplifier of the oscillator and the internal cloc k circuit. this is an alternative pin configuration of pc5. 1.1.4 xtal2 output from the inverting ampl ifier of the oscillator. altern ative pin configuration of pc4. 1.1.5 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and prov ided the reset pin has not been disabled. the min- imum pulse length is given in table 24-5 on page 246 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 1.1.6 port a (pa7:pa0) this is an 8-bit, bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). output buffers have the following drive characteristics: ? pa7, pa4:pa0: symmetrical, with sta ndard sink and source capability ? pa6, pa5: asymmetrical, with high si nk and standard source capability as inputs, port pins that are externally pulled low will source current pr ovided that pull-up resis- tors are activated. port pins are tri-stated when a reset co ndition becomes active, even if the clock is not running. this port has alternate pin functions to serve special features of the device. see ?alternate func- tions of port a? on page 67 . 1.1.7 port b (pb3:pb0) this is a 4-bit, bi-directional i/o port with internal pull-up resistors (selected for each bit).output buffers have the following drive characteristics: ? pb3: asymmetrical, with high sink and standard source capability ? pb2:pb0: symmetrical, with stan dard sink and source capability as inputs, port pins that are externally pulled low will source current pr ovided that pull-up resis- tors are activated. port pins are tri-stated when a reset co ndition becomes active, even if the clock is not running. this port has alternate pin functions to serve special features of the device. see ?alternate func- tions of port b? on page 70 . www.datasheet.co.kr datasheet pdf - http://www..net/
4 8303bs?avr?03/12 ATTINY1634 1.1.8 port c (pc5:pc0) this is a 6-bit, bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). output buffers have the following drive characteristics: ? pc5:pc1: symmetrical, with standard sink and source capability ? pc0: asymmetrical, with high sink and standard source capability as inputs, port pins that are externally pulled low will source current pr ovided that pull-up resis- tors are activated. port pins are tri-stated when a reset co ndition becomes active, even if the clock is not running. this port has alternate pin functions to serve special features of the device. see ?alternate func- tions of port c? on page 72 . www.datasheet.co.kr datasheet pdf - http://www..net/
5 8303bs?avr?03/12 ATTINY1634 2. overview ATTINY1634 is a low-power cmos 8-bit mi crocontrollers based on the avr enhanced risc architecture. by executing powerful instructions in a single clo ck cycle, the ATTINY1634 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power con- sumption versus processing speed. figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arit hmetic logic unit (alu), allowing two independent registers to be accessed in a sing le instruction, executed in on e clock cycle. the resulting archi- tecture is compact and code efficient while ac hieving throughputs up to ten times faster than conventional cisc microcontrollers. debug interface calibrated ulp oscillator watchdog timer calibrated oscillator timing and control v cc reset gnd 8-bit data bus cpu core program memory (flash) data memory (sram) power supervision: por bod reset isp interface port a port c port b voltage reference multiplexer analog comparator adc temperature sensor two-wire interface usart0 touch sensing eeprom on-chip debugger pc[5:0] pb[3:0] pa[7:0] 8-bit timer/counter 16-bit timer/counter usi usart1 www.datasheet.co.kr datasheet pdf - http://www..net/
6 8303bs?avr?03/12 ATTINY1634 ATTINY1634 provides the following features: ? 16k bytes of in-system programmable flash ? 1k bytes of sram data memory ? 256 bytes of eeprom data memory ? 18 general purpose i/o lines ? 32 general purpose working registers ? an 8-bit timer/counter with two pwm channels ? a16-bit timer/counter with two pwm channels ? internal and external interrupts ? a 10-bit adc with 5 internal and 12 external chanels ? an ultra-low power, programmable wa tchdog timer with internal oscillator ? two programmable usart?s with start frame detection ? a slave two-wire interface (twi) ? a universal serial interface (usi) with start condition detector ? a calibrated 8mhz oscillator ? a calibrated 32khz, ultra low power oscillator ? four software selectable power saving modes. the device includes the following modes for saving power: ? idle mode: stops the cpu while allowing the timer/counter, adc, analog comparator, spi, twi, and interrupt system to continue functioning ? adc noise reduction mode: minimizes switchin g noise during adc conversions by stopping the cpu and all i/o modules except the adc ? power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset ? standby mode: the oscillator is running while the rest of the de vice is sleeping, allowing very fast start-up combined wit h low power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the flash program memory can be re-programmed in-s ystem through a serial interface, by a con- ventional non-volatile memory programmer or by an on-chip boot code, running on the avr core. the ATTINY1634 avr is supported by a full suit e of program and system development tools including: c compilers, macro assemblers, program debugger/simulators and evaluation kits. www.datasheet.co.kr datasheet pdf - http://www..net/
7 8303bs?avr?03/12 ATTINY1634 3. general information 3.1 resources a comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for downloa d at http://www.a tmel.com/avr. 3.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in the extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically, this means ?lds? and ?sts? combined with ?sbrs?, ?s brc?, ?sbr?, and ?cbr?. note that not all avr devices include an extended i/o map. 3.3 capacitive touch sensing atmel qtouch library provides a simple to use solution for touch sensitive interfaces on atmel avr microcontrollers. the qtouch library includes support for qtouch ? and qmatrix ? acquisi- tion methods. touch sensing is easily added to any application by linking the qtouch library and using the application programming interface (api) of the library to define the touch channels and sensors. the application then calls the api to retrieve ch annel information and determine the state of the touch sensor. the qtouch library is free and can be downloaded from the atmel website. for more informa- tion and details of implementation, refer to the qtouch library user guide ? also available from the atmel website. 3.4 data retention reliability qualification results sh ow that the projected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. www.datasheet.co.kr datasheet pdf - http://www..net/
8 8303bs?avr?03/12 ATTINY1634 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s) (0xff)reserved???????? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? ... ... ... ... ... ... ... ... ... ... ... (0x85) reserved ? ? ? ? ? ? ? ? (0x84) reserved ? ? ? ? ? ? ? ? (0x83) reserved ? ? ? ? ? ? ? ? (0x82) reserved ? ? ? ? ? ? ? ? (0x81) reserved ? ? ? ? ? ? ? ? (0x80) reserved ? ? ? ? ? ? ? ? (0x7f) twscra twshe ? twdie twasie twen twsie twpme twsme 135 (0x7e) twscrb twaa twcmd[1:0] 136 (0x7d) twssra twdif twasif twch twra twc twbe twdir twas 137 (0x7c) twsa twi slave address register 138 (0x7b) twsam twi slave address mask register 139 (0x7a) twsd twi slave data register 139 (0x79) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 178 (0x78) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 179 (0x77) ucsr1c umsel11 umsel10 upm11 upm01 usbs1 usbsz11 ucsz10 ucpol1 180 (0x76) ucsr1d rxsie1 rxs1 sfde1 182 (0x75) ubrr1h usart1 baud rate register high byte 183 (0x74) ubrr1l usart1 baud rate register low byte 183 (0x73) udr1 usart1 i/o data register 177 (0x72) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 117 (0x71) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 119 (0x70) tccr1c foc1a foc1b ? ? ? ? ? ? 120 (0x6f) tcnt1h timer/counter1 ? counter register high byte 121 (0x6e) tcnt1l timer/counter1 ? counter register low byte 121 (0x6d) ocr1ah timer/counter1 ? compare register a high byte 121 (0x6c) ocr1al timer/counter1 ? compare register a low byte 121 (0x6b) ocr1bh timer/counter1 ? compare register b high byte 121 (0x6a) ocr1bl timer/counter1 ? compare register b low byte 121 (0x69) icr1h timer/counter1 ? input capture register high byte 122 (0x68) icr1l timer/counter1 ? input capture register low byte 122 (0x67) gtccr tsm ? ? ? ? ? ? psr10 126 (0x66) osccal1 ? ? ? ? ? ?cal11cal10 36 (0x65) osctcal0b oscillator temperature compensation register b 36 (0x64) osctcal0a oscillator temperature compensation register a 35 (0x63) osccal0 cal07 cal06 cal05 cal04 cal03 cal02 cal01 cal00 35 (0x62) didr2 ? ? ? ? ? adc11d adc10d adc9d 213 (0x61) didr1 ? ? ? ? adc8d adc7d adc6d adc5d 213 (0x60) didr0 adc4d adc3d adc2d adc1d adc0d ain1d ain0d arefd 196 , 213 0x3f (0x5f) sreg i t h s v n z c 15 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 15 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 15 0x3c (0x5c) gimsk ? int0 pcie2 pcie1 pcie0 ? ? ? 56 0x3b (0x5b) gifr ? intf0 pcif2 pcif1 pcif0 ? ? ? 57 0x3a (0x5a) timsk toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a 94 , 122 0x39 (0x59) tifr tov1 ocf1a ocf1b ? icf1 ocf0b tov0 ocf0a 95 , 123 0x38 (0x58) qtcsr qtouch control and status register 7 0x37 (0x57) spmcsr ? ? rsig ctpb rflb pgwrt pgers spmen 219 0x36 (0x56) mcucr ?sm1sm0se ? ?isc01isc00 40 , 56 0x35 (0x55) mcusr ? ? ? ? wdrf borf extrf porf 49 0x34 (0x54) prr ? prtwi prtim0 prtim0 prusi prusart1 prusart0 pradc 41 0x33 (0x53) clkpr ? ? ? ? clkps3 clkps2 clkps1 clkps0 33 0x32 (0x52) clksr oscrdy cstr ckout_io sut cksel3 cksel2 cksel1 cksel0 32 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) wdtcsr wdif wdie wdp3 ? wde wdp2 wdp1 wdp0 50 0x2f (0x4f) ccp cpu change protection register 14 0x2e (0x4e) dwdr dwdr[7:0] 215 www.datasheet.co.kr datasheet pdf - http://www..net/
9 8303bs?avr?03/12 ATTINY1634 note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accesse d. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specif ied bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 0x2d (0x4d) usibr usi buffer register 153 0x2c (0x4c) usidr usi data register 153 0x2b (0x4b) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 152 0x2a (0x4a) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 149 0x29 (0x49) pcmsk2 ? ? pcint17 pcint16 pcint15 pcint14 pcint13 pcint12 58 0x28 (0x48) pcmsk1 ? ? ? ? pcint11 pcint10 pcint9 pcint8 58 0x27 (0x47) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 58 0x26 (0x46) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm 178 0x25 (0x45) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 179 0x24 (0x44) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 180 0x23 (0x43) ucsr0d rxcie0 rxs0 sfde0 ? ? ? ? ?182 0x22 (0x42) ubrr0h ? ? ? ? usart0 baud rate register high byte 183 0x21 (0x41) ubrr0l usart0 baud rate register low byte 183 0x20 (0x40) udr0 usart0 i/o data register 177 0x1f (0x3f) eearh ? ? ? ? ? ? ? ? 0x1e (0x3e) eearl eear[7:0] 24 0x1d (0x3d) eedr eeprom data register 24 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 25 0x1b (0x3b) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 89 0x1a (0x3a) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 92 0x19 (0x39) tcnt0 timer/counter0 93 0x18 (0x38) ocr0a timer/counter0 ? compare register a 94 0x17 (0x37) ocr0b timer/counter0 ? compare register b 94 0x16 (0x36) gpior2 general purpose register 2 26 0x15 (0x35) gpior1 general purpose register 1 26 0x14 (0x34) gpior0 general purpose register 0 26 0x13 (0x33) portcr ? ? ? ? ? bbmc bbmb bbma 75 0x12 (0x32) puea puea7 puea6 puea5 puea4 puea3 puea2 puea1 puea0 76 0x11 (0x31) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 76 0x10 (0x30) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 76 0x0f (0x2f) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 76 0x0e (0x2e) pueb ? ? ? ? pueb3 pueb2 pueb1 pueb0 76 0x0d (0x2d) portb ? ? ? ? portb3 portb2 portb1 portb0 76 0x0c (0x2c) ddrb ? ? ? ? ddb3 ddb2 ddb1 ddb0 76 0x0b (0x2b) pinb ? ? ? ? pinb3 pinb2 pinb1 pinb0 77 0x0a (0x2a) puec ? ? puec5 puec4 puec3 puec2 puec1 puec0 77 0x09 (0x29) portc ? ? portc5 portc4 portc3 portc2 portc1 portc0 77 0x08 (0x28) ddrc ? ? ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 77 0x07 (0x27) pinc ? ? pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 77 0x06 (0x26) acsra acd acbg aco aci acie acic acis1 acis0 194 0x05 (0x25) acsrb hsel hlev aclp ? acce acme acirs1 acirs0 195 0x04 (0x24) admux refs1 refs0 refen adc0en mux3 mux2 mux1 mux0 208 0x03 (0x23) adcsra aden adsc adate adif adie adps2 adps1 adps0 210 0x02 (0x22) adcsrb vden vdpd ? ? adlar adts2 adts1 adts0 212 0x01 (0x21) adch adc data register high byte 211 0x00 (0x20) adcl adc data register low byte 211 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s) www.datasheet.co.kr datasheet pdf - http://www..net/
10 8303bs?avr?03/12 ATTINY1634 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions jmp k direct jump pc knone3 rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 call k direct subroutine pc knone4 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 www.datasheet.co.kr datasheet pdf - http://www..net/
11 8303bs?avr?03/12 ATTINY1634 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks www.datasheet.co.kr datasheet pdf - http://www..net/
12 8303bs?avr?03/12 ATTINY1634 6. ordering information notes: 1. for speed vs. supply voltage, see section 24.3 ?speed? on page 244 . 2. all packages are pb-free, halide-free and fully green, and they comply with the eur opean directive for restriction of hazard- ous substances (rohs). 3. denotes accuracy of the internal oscillator. see table 24-2 on page 244 . 4. code indicators: ? u: matte tin ? r: tape & reel 5. can also be supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 6.1 ATTINY1634 speed (mhz) (1) supply voltage (v) temperature range package (2) accuracy (3) ordering code (4) 12 1.8 ? 5.5 industrial (-40 c to +85 c) (5) 20m1 10% ATTINY1634-mu 2% ATTINY1634r-mu 10% ATTINY1634-mur 2% ATTINY1634r-mur 20s2 10% ATTINY1634-su 2% ATTINY1634r-su 10% ATTINY1634-sur 2% ATTINY1634r-sur package type 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no- lead / micro lead frame package (qfn/mlf) 20s2 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) www.datasheet.co.kr datasheet pdf - http://www..net/
13 8303bs?avr?03/12 ATTINY1634 7. packaging information 7.1 20m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20m1 , 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0.50 mm, b 20m1 10/27/04 2.6 mm exposed pad, micro lead frame package (mlf) a 0.70 0.75 0.80 a1 ? 0.01 0.05 a2 0.20 ref b 0.18 0.23 0.30 d 4.00 bsc d2 2.45 2.60 2.75 e 4.00 bsc e2 2.45 2.60 2.75 e 0.50 bsc l 0.35 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec standard mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of measure = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.08 c l 1 2 3 b 1 2 3 www.datasheet.co.kr datasheet pdf - http://www..net/
14 8303bs?avr?03/12 ATTINY1634 7.2 20s2 www.datasheet.co.kr datasheet pdf - http://www..net/
15 8303bs?avr?03/12 ATTINY1634 8. errata the revision letters in this sect ion refer to the revision of the corresponding ATTINY1634 device. 8.1 ATTINY1634 8.1.1 rev. b ? port pin should not be used as input when ulp oscillator is disabled 1. port pin should not be used as input when ulp oscillator is disabled port pin pb3 is not guaranteed to perform as a reliable input when the ultra low power (ulp) oscillator is not running. in addition, the pin is pulled down internally when ulp oscil- lator is disabled. problem fix / workaround the ulp oscillator is automatically activated when required. to use pb3 as an input, acti- vate the watchdog timer. the watchdog time r automatically enables the ulp oscillator. 8.1.2 rev. a ? flash / eeprom can not be written wh en supply voltag e is below 2.4v ? port pin should not be used as input when ulp oscillator is disabled 1. flash / eeprom can not be written when supply voltage is below 2.4v when supply voltage is below 2.4v writ e operations to flash and eeprom may fail. problem fix / workaround do not write to flash or eeprom wh en supply voltage is below 2.4v. 2. port pin should not be used as input when ulp oscillator is disabled port pin pb3 is not guaranteed to perform as a reliable input when the ultra low power (ulp) oscillator is not running. in addition, the pin is pulled down internally when ulp oscil- lator is disabled. problem fix / workaround the ulp oscillator is automatically activated when required. to use pb3 as an input, acti- vate the watchdog timer. the watchdog time r automatically enables the ulp oscillator. www.datasheet.co.kr datasheet pdf - http://www..net/
16 8303bs?avr?03/12 ATTINY1634 9. datasheet revision history 9.1 rev. 8303b ? 03/12 1. removed preliminary status. 2. added: ? ?typical characteristics? on page 253 ? ?temperature sensor? on page 249 ? ?rev. b? on page 294 3. updated: ? ?pin descriptions? on page 3 ? ?calibrated internal 8mhz oscillator? on page 29 ? ?osctcal0a ? oscillator temperature calibration register a? on page 35 ? ?osctcal0b ? oscillator temperature calibration register b? on page 36 ? ?twscra ? twi slave control register a? on page 135 ? ?usart (usart0 & usart1)? on page 154 ? ?temperature vs. sensor output voltage (typical)? on page 208 ? ?dc characteristics? on page 242 ? ?calibration accuracy of internal 32khz oscillato r? on page 245 ? ?external clock drive characteristics? on page 245 ? ?reset, brown-out, and internal voltage characteristics? on page 246 ? ?analog comparator characteristics, ta = -40c to +85c? on page 249 ? ?parallel programming characteristics, ta = 25c, vcc = 5v? on page 250 ? ?serial programming characteristics, ta = -40c to +85c? on page 252 ? ?ordering information? on page 291 9.2 rev. 8303a ? 11/11 initial revision. www.datasheet.co.kr datasheet pdf - http://www..net/
17 8303bs?avr?03/12 ATTINY1634 www.datasheet.co.kr datasheet pdf - http://www..net/
8303bs?avr?03/12 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81)(3) 3523-3551 fax: (+81)(3) 3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection wi th atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including , but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indire ct, consequential, punitive, special or i nciden- tal damages (including, without li mitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of th is document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2012 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. o ther terms and product names may be trademarks of others. www.datasheet.co.kr datasheet pdf - http://www..net/

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